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CRC Generator for Verilog or VHDL

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Description

CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible.

There is an online version of CRC generator that can generate Verilog or VHDL code for CRC for smaller range of data width and polynomial inputs.

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Parameters

language: verilog or vhdl

data_width : data bus width {1..1024}

poly_width : polynomial width {1..1024}

poly_string : a string that describes CRC polynomial.

Examples: 05 = x⁵+x²+1

8005 = x¹⁶ + x¹⁵+ x²+ 1

Note: string representation (0x05, 0x8005) doesn’t include highest degree coefficient in polynomial representation (x⁵ and x¹⁶ in the above examples)

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Output Examples

[1] C:\OutputLogic\lfsr-counter-generator> lfsr-counter-generator

usage:

lfsr-counter-generator language count

parameters:

language: verilog or vhdl

count : counter value in hex or decimal format, e.g. 1234, 0x1234

[2] C:\OutputLogic> lfsr-counter-generator verilog 0x1234

count = 0x1234 num_bits=13

generating...

//-----------------------------------------------------------------------------

// Copyright (C) 2009 OutputLogic.com

// This source file may be used and distributed without restriction

// provided that this copyright statement is not removed from the file

// and that any derivative work contains the original copyright notice

// and the associated disclaimer. --

// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS

// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED

// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.

//-----------------------------------------------------------------------------

module lfsr_counter(

input clk,

input reset,

input ce,

output reg lfsr_done);

reg [12:0] lfsr;

wire d0,lfsr_equal;

xnor(d0,lfsr[12],lfsr[3],lfsr[2],lfsr[0]);

assign lfsr_equal = (lfsr == 13'h220);

always @(posedge clk,posedge reset) begin

if(reset) begin

lfsr <= 0;

lfsr_done <= 0;

end

else begin

if(ce)

lfsr <= lfsr_equal ? 13'h0 : {lfsr[11:0],d0};

lfsr_done <= lfsr_equal;

end

end

endmodule

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Downloads

Executable and source code from SourceForge.net

Article on parallel CRC generation method used in this project.

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About the Author

Evgeni Stavinov is the creator and main developer of OutputLogic.com. Evgeni has more than 10 years of diverse design experience in the areas of FPGA logic design, embedded software and communication protocols. He holds MSEE from University of Southern California and BSEE from Technion – Israel Institute of Technology. For more information contact evgeni@outputlogic.com

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About OutputLogic.com

OutputLogic.com is a web portal that offers online tools for FPGA and ASIC designers.

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